View SC68C752B_6046782.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the SC68C752B is a dual universal asynchronous receiver/transmitter (uart) with 64-byte fifos, automatic hardware/software ?ow control, and data rates up to 5 mbit/s. the SC68C752B offers enhanced features. it has a transmission control register (tcr) that stores receiver fifo threshold levels to start/stop transmission during hardware and software ?ow control. with the fifo rdy register, the software gets the status of txrd y/ rxrd y for all four ports in one access. on-chip status registers provide the user with error indications, operational status, and modem interface control. system interrupts may be tailored to meet user requirements. an internal loop-back capability allows on-board diagnostics. the uart transmits data, sent to it over the peripheral 8-bit bus, on the tx signal and receives characters on the rx signal. characters can be programmed to be 5, 6, 7, or 8 bits. the uart has a 64-byte receive fifo and transmit fifo and can be programmed to interrupt at different trigger levels. the uart generates its own desired baud rate based upon a programmable divisor and its input clock. it can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. the receiver can detect break, idle, or framing errors, fifo over?ow, and parity errors. the transmitter can detect fifo under?ow. the uart also contains a software interface for modem control operations, and has software ?ow control and hardware ?ow control capabilities. the SC68C752B is available in a plastic lqfp48 package. 2. features n dual channel with motorola m p interface n up to 5 mbit/s data rate n 64-byte transmit fifo n 64-byte receive fifo with error ?ags n programmable and selectable transmit and receive fifo trigger levels for dma and interrupt generation n software/hardware ?ow control u programmable xon/xoff characters u programmable auto- r ts and auto- cts n optional data ?ow resume by xon any character n dma signalling capability for both received and transmitted data n supports 5 v, 3.3 v and 2.5 v operation n 5 v tolerant inputs n software selectable baud rate generator SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos and motorola m p interface rev. 02 28 april 2005 product data sheet
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 2 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos n prescaler provides additional divide-by-4 function n industrial temperature range ( - 40 c to +85 c) n fast data bus access time n programmable sleep mode n programmable serial interface characteristics u 5, 6, 7, or 8-bit characters u even, odd, or no parity bit generation and detection u 1, 1.5, or 2 stop bit generation n false start bit detection n complete status reporting capabilities in both normal and sleep mode n line break generation and detection n internal test and loop-back capabilities n fully prioritized interrupt system controls n modem control functions ( cts, r ts, dsr, dtr, ri, and cd) 3. ordering information table 1: ordering information type number package name description version SC68C752Bib48 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 3 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 4. block diagram fig 1. block diagram of SC68C752B txa, txb rxa, rxb SC68C752B xtal2 xtal1 d0 to d7 r/w reset 002aab017 data b u s and control logic register select logic a0 to a3 cs interrupt control logic irq txrdya, txrdyb rxrdya, rxrdyb clock and baud rate generator interconnect bus lines and control signals modem control logic dtrs, dtrb rtsa, rtsb opa, opb ctsa, ctsb ria, rib cda, cdb dsra, dsrb receive shift register receive fifo register flow control logic flow control logic transmit shift register transmit fifo register
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 4 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 5. pinning information 5.1 pinning 5.2 pin description fig 2. pin con?guration for lqfp48 SC68C752Bib48 d5 reset d6 dtrb d7 dtra rxb rtsa rxa opa txrdyb rxrdya txa irq txb n.c. opb a0 cs a1 a3 a2 n.c. n.c. xtal1 d4 xtal2 d3 r/w d2 cdb d1 gnd d0 rxrdyb txrdya v cc v cc dsrb ria rib cda rtsb dsra ctsb gnd ctsa n.c. 002aab018 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 table 2: pin description symbol pin type description a0 28 i address 0 select bit. internal registers address selection. a1 27 i address 1 select bit. internal registers address selection. a2 26 i address 2 select bit. internal registers address selection. a3 11 i address 3. a3 is used to select channel a or channel b. a logic low selects channel a, and a logic high selects channel b. (see t ab le 3 .) cd a, cdb 40, 16 i carrier detect (active low). these inputs are associated with individual uart channel a and channel b. a logic low on these pins indicates that a carrier has been detected by the modem for that channel. the state of these inputs is re?ected in the modem status register (msr). cs 10 i chip select (active low). this pin enables data transfers between the user cpu and the SC68C752B for the channel(s) addressed. individual uart sections (a, b) are addressed by a3. see t ab le 3 . ctsa, ctsb 38, 23 i clear to send (active low). these inputs are associated with individual uart channel a and channel b. a logic 0 (low) on the cts pins indicates the modem or data set is ready to accept transmit data from the SC68C752B. status can be tested by reading msr[4]. these pins only affect the transmit and receive operations when auto- cts function is enabled via the enhanced feature register efr[7] for hardware ?ow control operation.
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 5 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos d0 to d7 44, 45, 46, 47, 48, 1, 2, 3 i/o data bus (bi-directional). these pins are the 8-bit, 3-state data bus for transferring information to or from the controlling cpu. d0 is the least signi?cant bit and the ?rst data bit in a transmit or receive serial data stream. dsra, dsrb 39, 20 i data set ready (active low). these inputs are associated with individual uart channel a and channel b. a logic 0 (low) on these pins indicates the modem or data set is powered-on and is ready for data exchange with the uart. the state of these inputs is re?ected in the modem status register (msr). dtra, dtrb 34, 35 o data terminal ready (active low). these outputs are associated with individual uart channel a and channel b. a logic 0 (low) on these pins indicates that the SC68C752B is powered-on and ready. these pins can be controlled via the modem control register. writing a logic 1 to mcr[0] will set the dtr output to logic 0 (low), enabling the modem. the output of these pins will be a logic 1 after writing a logic 0 to mcr[0], or after a reset. gnd 17, 24 i signal and power ground. irq 30 o interrupt request. interrupts from uart channel a and channel b are wire-ored internally to function as a single irq interrupt. this pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a uart channel(s) requires service. individual channel interrupt status can be determined by addressing each channel through its associated internal register, using cs and a3. an external pull-up resistor must be connected between this pin and v cc . r/ w 15 i a logic low on this pin will transfer the contents of the data bus (d[0:7]) from an external cpu to an internal register that is de?ned by address bits a[0:2]. a logic high on this pin will load the contents of an internal register de?ned by address bits a[0:2] on the SC68C752B data bus (d[0:7]) for access by an external cpu. n.c. 12, 25, 29, 37 - not connected. op a, opb 32, 9 o user de?ned outputs. this function is associated with individual channel a and channel b. the state of these pins is de?ned by the user through the software settings of mcr[3]. op a/ opb is a logic 0 when mcr[3] is set to a logic 1. op a/ opb is a logic 1 when mcr[3] is set to a logic 0. the output of these two pins is high after reset. reset 36 i reset (active low). this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. reset is an active low input. ria, rib 41, 21 i ring indicator (active low). these inputs are associated with individual uart channel a and channel b. a logic 0 on these pins indicates the modem has received a ringing signal from the telephone line. a low-to-high transition on these input pins generates a modem status interrupt, if enabled. the state of these inputs is re?ected in the modem status register (msr). r tsa, r tsb 33, 22 o request to send (active low). these outputs are associated with individual uart channel a and channel b. a logic 0 on the r ts pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register mcr[1] will set this pin to a logic 0, indicating data is available. after a reset these pins are set to a logic 1. these pins only affect the transmit and receive operations when auto- r ts function is enabled via the enhanced feature register (efr[6]) for hardware ?ow control operation. rxa, rxb 5, 4 i receive data input. these inputs are associated with individual serial channel data to the SC68C752B. during the local loop-back mode, these rx input pins are disabled and tx data is connected to the uart rx input internally. table 2: pin description continued symbol pin type description
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 6 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos rxrd y a, rxrd yb 31, 18 o receive ready (active low). rxrd y a or rxrd yb goes low when the trigger level has been reached or the fifo has at least one character. it goes high when the rx fifo is empty. txa, txb 7, 8 o transmit data a, b. these outputs are associated with individual serial transmit channel data from the SC68C752B. during the local loop-back mode, the tx output pin is disabled and tx data is internally connected to the uart rx input. txrd y a, txrd yb 43, 6 o transmit ready (active low). txrd y aor txrd yb go low when there are at least a trigger level number of spaces available or when the fifo is empty. it goes high when the fifo is full or not empty. v cc 19, 42 i power supply input. xtal1 13 i crystal or external clock input. functions as a crystal input or as an external clock input. a crystal can be connected between xtal1 and xtal2 to form an internal oscillator circuit (see figure 12 ). alternatively, an external clock can be connected to this pin to provide custom data rates. xtal2 14 o output of the crystal oscillator or buffered clock. (see also xtal1.) xtal2 is used as a crystal oscillator output or a buffered clock output. table 2: pin description continued symbol pin type description table 3: channel selection using cs pin cs a3 uart channel 1 - none 0 0 channel a 0 1 channel b
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 7 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6. functional description the uart will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. the complete status of each channel of the SC68C752B uart can be read at any time during functional operation by the processor. the SC68C752B can be placed in an alternate mode (fifo mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. both the receiver and transmitter fifos can store up to 64 bytes (including three additional bits of error status per byte for the receiver fifo) and have selectable or programmable trigger levels. primary outputs rxrd y and txrd y allow signalling of dma transfers. the SC68C752B has selectable hardware ?ow control and software ?ow control. hardware ?ow control signi?cantly reduces software overhead and increases system ef?ciency by automatically controlling serial data ?ow using the r ts output and cts input signals. software ?ow control automatically controls data ?ow by using programmable xon/xoff characters. the uart includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (2 16 - 1). 6.1 trigger levels the SC68C752B provides independent selectable and programmable trigger levels for both receiver and transmitter dma and interrupt generation. after reset, both transmitter and receiver fifos are disabled and so, in effect, the trigger level is the default value of one byte. the selectable trigger levels are available via the fcr. the programmable trigger levels are available via the trigger level register (tlr). 6.2 hardware ?ow control hardware ?ow control is comprised of auto- cts and auto- r ts. auto- cts and auto- r ts can be enabled/disabled independently by programming efr[7:6]. with auto- cts, cts must be active before the uart can transmit data. auto- r ts only activates the r ts output when there is enough room in the fifo to receive data and de-activates the r ts output when the rx fifo is suf?ciently full. the halt and resume trigger levels in the tcr determine the levels at which r ts is activated/deactivated. if both auto- cts and auto- r ts are enabled, when r ts is connected to cts, data transmission does not occur unless the receiver fifo has empty space. thus, overrun errors are eliminated during hardware ?ow control. if not enabled, overrun errors occur if the transmit data rate exceeds the receive fifo servicing latency.
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 8 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.2.1 auto- r ts auto- r ts data ?ow control originates in the receiver block (see figure 1 bloc k diag r am of SC68C752B on page 3 ). figure 4 shows r ts functional timing. the receiver fifo trigger levels used in auto- r ts are stored in the tcr. r ts is active if the rx fifo level is below the halt trigger level in tcr[3:0]. when the receiver fifo halt trigger level is reached, r ts is de-asserted. the sending device (for example, another uart) may send an additional byte after the trigger level is reached (assuming the sending uart has another byte to send) because it may not recognize the de-assertion of r ts until it has begun sending the additional byte. r ts is automatically reasserted once the receiver fifo reaches the resume trigger level programmed via tcr[7:4]. this re-assertion allows the sending device to resume transmission. fig 3. auto ?ow control (auto- r ts and auto- cts) example rx fifo flow control tx fifo parallel to serial tx fifo rx fifo uart 1 uart 2 d7 to d0 rx tx rts cts tx rx cts rts d7 to d0 002aaa228 serial to parallel serial to parallel flow control flow control flow control parallel to serial (1) n = receiver fifo trigger level. (2) the two blocks in dashed lines cover the case where an additional byte is sent, as described in section 6.2.1 . fig 4. r ts functional timing start byte n start byte n + 1 start stop stop rx rts r/w nn + 1 12 002aab086
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 9 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.2.2 auto- cts the transmitter circuitry checks cts before sending the next data byte. when cts is active, the transmitter sends the next byte. to stop the transmitter from sending the following byte, cts must be de-asserted before the middle of the last stop bit that is currently being sent. the auto- cts function reduces interrupts to the host system. when ?ow control is enabled, cts level changes do not trigger host interrupts because the device automatically controls its own transmitter. without auto- cts, the transmitter sends any data present in the transmit fifo and a receiver overrun error may result. 6.3 software ?ow control software ?ow control is enabled through the enhanced feature register and the modem control register. different combinations of software ?ow control can be enabled by setting different combinations of efr[3:0]. t ab le 4 shows software ?ow control options. (1) when cts is low, the transmitter keeps sending serial data out. (2) when cts goes high before the middle of the last stop bit of the current byte, the transmitter ?nishes sending the current byte, but is does not send the next byte. (3) when cts goes from high to low, the transmitter begins sending data again. fig 5. cts functional timing start byte 0 to 7 stop tx cts 002aaa227 start byte 0 to 7 stop table 4: software ?ow control options (efr[0:3]) efr[3] efr[2] efr[1] efr[0] tx, rx software ?ow controls 0 0 x x no transmit ?ow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1, xon2, xoff1, xoff2 x x 0 0 no receive ?ow control x x 1 0 receiver compared xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1011tr ansmit xon1, xoff1 receiver compares xon1 and xon2, xoff1 and xoff2 0111tr ansmit xon2, xoff2 receiver compares xon1 and xon2, xoff1 and xoff2 1111tr ansmit xon1, xon2, xoff1, xoff2 receiver compares xon1 and xon2, xoff1 and xoff2
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 10 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos there are two other enhanced features relating to software ?ow control: ? xon any function (mcr[5]): operation will resume after receiving any character after recognizing the xoff character. it is possible that an xon1 character is recognized as an xon any character, which could cause an xon2 character to be written to the rx fifo. ? special character (efr[5]): incoming data is compared to xoff2. detection of the special character sets the xoff interrupt (iir[4]) but does not halt transmission. the xoff interrupt is cleared by a read of the iir. the special character is transferred to the rx fifo. 6.3.1 rx when software ?ow control operation is enabled, the SC68C752B will compare incoming data with xoff1,2 programmed characters (in certain cases, xoff1 and xoff2 must be received sequentially). when the correct xoff character are received, transmission is halted after completing transmission of the current character. xoff detection also sets iir[4] (if enabled via ier[5]) and causes irq to go high. to resume transmission, an xon1,2 character must be received (in certain cases xon1 and xon2 must be received sequentially). when the correct xon characters are received, iir[4] is cleared, and the xoff interrupt disappears. 6.3.2 tx xoff1/2 character is transmitted when the rx fifo has passed the halt trigger level programmed in tcr[3:0]. xon1/2 character is transmitted when the rx fifo reaches the resume trigger level programmed in tcr[7:4]. the transmission of xoff/xon(s) follows the exact same protocol as transmission of an ordinary byte from the fifo. this means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least signi?cant bits of xoff1,2/xon1,2 will be transmitted. (note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.) it is assumed that software ?ow control and hardware ?ow control will never be enabled simultaneously. figure 6 shows an example of software ?ow control.
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 11 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.3.3 software ?ow control example 6.3.3.1 assumptions uart1 is transmitting a large text ?le to uart2. both uarts are using software ?ow control with single character xoff (0f) and xon (0d) tokens. both have xoff threshold (tcr[3:0] = f) set to 60, and xon threshold (tcr[7:4] = 8) set to 32. both have the interrupt receive threshold (tlr[7:4] = d) set to 52. uart1 begins transmission and sends 52 characters, at which point uart2 will generate an interrupt to its processor to service the rcv fifo, but assume the interrupt latency is fairly long. uart1 will continue sending characters until a total of 60 characters have been sent. at this time, uart2 will transmit a 0f to uart1, informing uart1 to halt transmission. uart1 will likely send the 61 st character while uart2 is sending the xoff character. now uart2 is serviced and the processor reads enough data out of the rx fifo that the level drops to 32. uart2 will now send a 0d to uart1, informing uart1 to resume transmission. fig 6. software ?ow control example transmit fifo parallel-to-serial serial-to-parallel xon-1 word xon-2 word xoff-1 word xoff-2 word receive fifo parallel-to-serial serial-to-parallel xon-1 word xon-2 word xoff-1 word xoff-2 word uart2 uart1 002aaa229 data xoffCxonCxoff compare programmed xon-xoff characters
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 12 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.4 reset t ab le 5 summarizes the state of register after reset. remark: registers dll, dlh, spr, xon1, xon2, xoff1, xoff2 are not reset by the top-level reset signal reset, that is, they hold their initialization values during reset. t ab le 6 summarizes the state of registers after reset. table 5: register reset functions register reset control reset state interrupt enable register reset all bits cleared interrupt identi?cation register reset bit 0 is set; all other bits cleared fifo control register reset all bits cleared line control register reset reset to 00011101 (1dh) modem control register reset all bits cleared line status register reset bits 5 and 6 set; all other bits cleared modem status register reset bits 0 to 3 cleared; bits 4 to 7 input signals enhanced feature register reset all bits cleared receiver holding register reset pointer logic cleared transmitter holding register reset pointer logic cleared transmission control register reset all bits cleared trigger level register reset all bits cleared table 6: signal reset functions signal reset control reset state tx reset high r ts reset high dtr reset high rxrd y reset high txrd y reset low
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 13 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.5 interrupts the SC68C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. the interrupt enable register (ier) enables each of the six types of interrupts and the irq signal in response to an interrupt generation. the ier can also disable the interrupt system by clearing bits 0:3, 5:7. when an interrupt is generated, the iir indicates that an interrupt is pending and provides the type of interrupt through iir[5:0]. t ab le 7 summarizes the interrupt control functions. it is important to note that for the framing error, parity error, and break conditions, lsr[7] generates the interrupt. lsr[7] is set when there is an error anywhere in the rx fifo, and is cleared only when there are no more errors remaining in the fifo. lsr[4:2] always represent the error status for the received character at the top of the rx fifo. reading the rx fifo updates lsr[4:2] to the appropriate status for the new character at the top of the fifo. if the rx fifo is empty, then lsr[4:2] are all zeros. for the xoff interrupt, if an xoff ?ow character detection caused the interrupt, the interrupt is cleared by an xon ?ow character detection. if a special character detection caused the interrupt, the interrupt is cleared by a read of the iir. table 7: interrupt control functions iir[5:0] priority level interrupt type interrupt source interrupt reset method 000001 none none none none 000110 1 receiver line status oe, fe, pe, or bi errors occur in characters in the rx fifo fe, pe, bi: all erroneous characters are read from the rx fifo. oe: read lsr 001100 2 rx time-out stale data in rx fifo read rhr 000100 2 rhr interrupt drdy (data ready) (fifo disable) rx fifo above trigger level (fifo enable) read rhr 000010 3 thr interrupt tfe (thr empty) (fifo disable) tx fifo passes above trigger level (fifo enable) read iir or a write to the thr 000000 4 modem status msr[3:0] = 0 read msr 010000 5 xoff interrupt receive xoff character(s)/special character receive xon character(s)/read of iir 100000 6 cts, rts r ts pin or cts pin change state from active (low) to inactive (high) read iir
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 14 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.5.1 interrupt mode operation in interrupt mode (if any bit of ier[3:0] is 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, irq. therefore, it is not necessary to continuously poll the line status register (lsr) to see if any interrupt needs to be serviced. figure 7 shows interrupt mode operation. 6.5.2 polled mode operation in polled mode (ier[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the line status register (lsr). this mode is an alternative to the fifo interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the cpu. figure 8 shows fifo polled mode operation. fig 7. interrupt mode operation 11 11 iir ier thr rhr processor r/w irq 002aab096 fig 8. fifo polled mode operation 00 00 iir ier thr rhr processor r/w 002aab097
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 15 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.6 dma operation there are two modes of dma operation, dma mode 0 or dma mode 1, selected by fcr[3]. in dma mode 0 or fifo disable (fcr[0] = 0) dma occurs in single character transfers. in dma mode 1, multi-character (or block) dma transfers are managed to relieve the processor for longer periods of time. 6.6.1 single dma transfers (dma mode 0/fifo disable) figure 9 shows txrd y and rxrd y in dma mode 0/fifo disable. 6.6.1.1 transmitter when empty, the txrd y signal becomes active. txrd y will go inactive after one character has been loaded into it. 6.6.1.2 receiver rxrd y is active when there is at least one character in the fifo. it becomes inactive when the receiver is empty. fig 9. txrd y and rxrd y in dma mode 0/fifo disable tx wrptr wrptr fifo empty txrdy rx rdptr rdptr fifo empty rxrdy rxrdy 002aaa232 at least one location filled at least one location filled txrdy
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 16 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.6.2 block dma transfers (dma mode 1) figure 10 shows txrd y and rxrd y in dma mode 1. 6.6.2.1 transmitter txrd y is active when there is a trigger level number of spaces available. it becomes inactive when the fifo is full. 6.6.2.2 receiver rxrd y becomes active when the trigger level has been reached, or when a time-out interrupt occurs. it will go inactive when the fifo is empty or an error in the rx fifo is ?agged by lsr[7]. 6.7 sleep mode sleep mode is an enhanced feature of the SC68C752B uart. it is enabled when efr[4], the enhanced functions bit, is set and when ier[4] is set. sleep mode is entered when: ? the serial data input line, rx, is idle (see section 6.8 break and time-out conditions ). ? the tx fifo and tx shift register are empty. ? there are no interrupts pending except thr and time-out interrupts. remark: sleep mode will not be entered if there is data in the rx fifo. in sleep mode, the uart clock and baud rate clock are stopped. since most registers are clocked using these clocks, the power consumption is greatly reduced. the uart will wake up when any change is detected on the rx line, when there is any change in the state of the modem input pins, or if data is written to the tx fifo. remark: writing to the divisor latches, dll and dlh, to set the baud clock, must not be done during sleep mode. therefore, it is advisable to disable sleep mode using ier[4] before writing to dll or dlh. fig 10. txrd y and rxrd y in dma mode 1 tx wrptr wrptr txrdy fifo full txrdy rx rdptr rdptr fifo empty rxrdy rxrdy 002aaa234 trigger level trigger level at least one location filled
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 17 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.8 break and time-out conditions an rx idle condition is detected when the receiver line, rx, has been high for 4 character time. the receiver line is sampled midway through each bit. when a break condition occurs, the tx line is pulled low. a break condition is activated by setting lcr[6]. 6.9 programmable baud rate generator the SC68C752B uart contains a programmable baud generator that takes any clock input and divides it by a divisor in the range between 1 and (2 16 - 1). an additional divide-by-4 prescaler is also available and can be selected by mcr[7], as shown in figure 11 . the output frequency of the baud rate generator is 16 the baud rate. the formula for the divisor is: where: prescaler = 1, when mcr[7] is set to 0 after reset (divide-by-1 clock selected) prescaler = 4, when mcr[7] is set to 1 after reset (divide-by-4 clock selected). remark: the default value of prescaler after reset is divide-by-1. figure 11 shows the internal prescaler and baud rate generator circuitry. dll and dlh must be written to in order to program the baud rate. dll and dlh are the least signi?cant and most signi?cant byte of the baud rate divisor. if dll and dlh are both zero, the uart is effectively disabled, as no baud clock will be generated. remark: the programmable baud rate generator is provided to select both the transmit and receive clock rates. t ab le 8 and t ab le 9 show the baud rate and divisor correlation for crystal with frequency 1.8432 mhz and 3.072 mhz, respectively. figure 12 shows the crystal clock circuit reference. fig 11. prescaler and baud rate generator block diagram divisor xtal1 crystal input frequency prescaler --------------------------------------------------------------------------- ? ?? desired baud rate 16 () --------------------------------------------------------------------------------- = baud rate generator logic mcr[7] = 1 mcr[7] = 0 prescaler logic (divide-by-1) internal oscillator logic 002aaa233 xtal1 xtal2 input clock prescaler logic (divide-by-4) reference clock internal baud rate clock for transmitter and receiver
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 18 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos table 8: baud rates using a 1.8432 mhz crystal desired baud rate divisor used to generate 16 clock percent error difference between desired and actual 50 2304 75 1536 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 0.69 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 2.86 table 9: baud rates using a 3.072 mhz crystal desired baud rate divisor used to generate 16 clock percent error difference between desired and actual 50 2304 75 2560 110 1745 0.026 134.5 1428 0.034 150 1280 300 640 600 320 1200 160 1800 107 0.312 2000 96 2400 80 3600 53 0.628 4800 40 7200 27 1.23 9600 20 19200 10 38400 5
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 19 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7. register descriptions each register is selected using address lines a0, a1, a2, and in some cases, bits from other registers. the programming combinations for register selection are shown in t ab le 10 . [1] mcr[7] can only be modi?ed when efr[4] is set. [2] accessed by a combination of address pins and register bits. [3] accessible only when lcr[7] is logic 1. [4] accessible only when lcr is set to 10111111 (xbf). [5] accessible only when efr[4] = 1 and mcr[6] = 1, that is, efr[4] and mcr[6] are read/write enables. [6] accessible only when cs = 0, mcr[2] = 1, and loop-back is disabled (mcr[4] = 0). fig 12. crystal oscillator connections 002aaa870 c2 47 pf xtal1 xtal2 x1 1.8432 mhz c1 22 pf c2 33 pf xtal1 xtal2 1.5 k w x1 1.8432 mhz c1 22 pf table 10: register map - read/write properties a2 a1 a0 read mode write mode 0 0 0 receive holding register (rhr) transmit holding register (thr) 0 0 1 interrupt enable register (ier) interrupt enable register 0 1 0 interrupt identi?cation register (iir) fifo control register (fcr) 0 1 1 line control register (lcr) line control register 1 0 0 modem control register (mcr) [1] modem control register [1] 1 0 1 line status register (lsr) 1 1 0 modem status register (msr) 1 1 1 scratchpad register (spr) scratchpad register 0 0 0 divisor latch lsb (dll) [2] [3] divisor latch lsb [2] [3] 0 0 1 divisor latch msb (dlh) [2] [3] divisor latch msb [2] [3] 0 1 0 enhanced feature register (efr) [2] [4] enhanced feature register [2] [4] 1 0 0 xon1 word [2] [4] xon1 word [2] [4] 1 0 1 xon2 word [2] [4] xon2 word [2] [4] 1 1 0 xoff1 word [2] [4] xoff1 word [2] [4] 1 1 1 xoff2 word [2] [4] xoff2 word [2] [4] 1 1 0 transmission control register (tcr) [2] [5] transmission control register [2] [5] 1 1 1 trigger level register (tlr) [2] [5] trigger level register [2] [5] 1 1 1 fifo ready register [2] [6]
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 20 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos t ab le 11 lists and describes the SC68C752B internal registers. [1] these registers are accessible only when lcr[7] = 0. [2] this bit can only be modi?ed if register bit efr[4] is enabled, that is, if enhanced functions are enabled. [3] the special register set is accessible only when lcr[7] is set to a logic 1. table 11: SC68C752B internal registers a2 a1 a0 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/ write general register set [1] 0 0 0 rhr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r 0 0 0 thr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0 0 1 ier 0/ cts interrupt enable [2] 0/ r ts interrupt enable [2] 0/ xoff [2] 0/x sleep mode [2] modem status interrupt receive line status interrupt thr empty interrupt rx data available interrupt r/w 0 1 0 fcr rx trigger level (msb) rx trigger level (lsb) 0/tx trigger level (msb) [2] 0/tx trigger level (lsb) [2] dma mode select tx fifo reset rx fifo reset fifo enable w 0 1 0 iir fcr[0] fcr[0] 0/ cts, r ts 0/xoff interrupt priority bit 2 interrupt priority bit 1 interrupt priority bit 0 interrupt status r 0 1 1 lcr dlab break control bit set parity parity type select parity enable number of stop bits word length bit 1 word length bit 0 r/w 1 0 0 mcr 1 or 1 /4 clock [2] tcr and tlr enable [2] 0/xon any [2] 0/enable loop-back op a/ opb control fifo ready enable rts dtr r/w 1 0 1 lsr 0/error in rx fifo thr and tsr empty thr empty break interrupt framing error parity error overrun error data in receiver r 1 1 0 msr cd ri dsr cts d cd d ri d dsr d cts r 1 1 1 spr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 0 tcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 1 tlr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 1 fifo rdy 0 0 rx fifo b status rx fifo a status 0 0 tx fifo b status tx fifo a status r special register set [3] 0 0 0 dll bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 0 0 1 dlh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w enhanced register set [4] 0 1 0 efr auto cts auto r ts special character detect enable enhanced functions [2] software ?ow control bit 3 software ?ow control bit 2 software ?ow control bit 1 software ?ow control bit 0 r/w 1 0 0 xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 0 1 xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 0 xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 1 xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 21 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos [4] enhanced feature register; xon1/xon2 and xoff1/xoff2 are accessible only when lcr is set to bfh. remark: refer to the notes under t ab le 10 for more register access information. 7.1 receiver holding register (rhr) the receiver section consists of the receiver holding register (rhr) and the receiver shift register (rsr). the rhr is actually a 64-byte fifo. the rsr receives serial data from the rx terminal. the data is converted to parallel data and moved to the rhr. the receiver section is controlled by the line control register. if the fifo is disabled, location zero of the fifo is used to store the characters. remark: in this case, characters are overwritten if over?ow occurs. if over?ow occurs, characters are lost. the rhr also stores the error status bits associated with each character. 7.2 transmit holding register (thr) the transmitter section consists of the transmit holding register (thr) and the transmit shift register (tsr). the thr is actually a 64-byte fifo. the thr receives data and shifts it into the tsr, where it is converted to serial data and moved out on the tx terminal. if the fifo is disabled, the fifo is still used to store the byte. characters are lost if over?ow occurs.
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 22 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.3 fifo control register (fcr) this is a write-only register that is used for enabling the fifos, clearing the fifos, setting transmitter and receiver trigger levels, and selecting the type of dma signalling. t ab le 12 shows fifo control register bit settings. table 12: fifo control register bits description bit symbol description 7:6 fcr[7] (msb), fcr[6] (lsb) rcvr trigger. sets the trigger level for the rx fifo. 00 - 8 characters 01 - 16 characters 10 - 56 characters 11 - 60 characters 5:4 fcr[5] (msb), fcr[4] (lsb) tx trigger. sets the trigger level for the tx fifo. 00 - 8 spaces 01 - 16 spaces 10 - 32 spaces 11 - 56 spaces fcr[5:4] can only be modi?ed and enabled when efr[4] is set. this is because the transmit trigger level is regarded as an enhanced function. 3 fcr[3] dma mode select. logic 0 = set dma mode 0 logic 1 = set dma mode 1 2 fcr[2] reset tx fifo. logic 0 = no fifo transmit reset (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 1 fcr[1] reset rx fifo. logic 0 = no fifo receive reset (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 0 fcr[0] fifo enable. logic 0 = disable the transmit and receive fifo (normal default condition) logic 1 = enable the transmit and receive fifo
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 23 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.4 line control register (lcr) this register controls the data communication format. the word length, number of stop bits, and parity type are selected by writing the appropriate bits to the lcr. t ab le 13 shows the line control register bit settings. table 13: line control register bits description bit symbol description 7 lcr[7] divisor latch enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 lcr[6] break control bit. when enabled, the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr[6] to a logic 0. logic 0 = no tx break condition (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 to alert the communication terminal to a line break condition 5 lcr[5] set parity. lcr[5] selects the forced parity format (if lcr[3] = 1). logic 0 = parity is not forced (normal default condition) lcr[5] = logic 1 and lcr[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data. lcr[5] = logic 1 and lcr[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data. 4 lcr[4] parity type select. logic 0 = odd parity is generated (if lcr[3] = 1). logic 1 = even parity is generated (if lcr[3] = 1). 3 lcr[3] parity enable. logic 0 = no parity (normal default condition). logic 1 = a parity bit is generated during transmission and the receiver checks for received parity. 2 lcr[2] number of stop bits. speci?es the number of stop bits. 0 = 1 stop bit (word length = 5, 6, 7, 8) 1 = 1.5 stop bits (word length = 5) 1 = 2 stop bits (word length = 6, 7, 8) 1:0 lcr[1:0] word length bits 1, 0. these two bits specify the word length to be transmitted or received. 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 24 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.5 line status register (lsr) t ab le 14 shows the line status register bit settings. when the lsr is read, lsr[4:2] re?ect the error bits (bi, fe, pe) of the character at the top of the rx fifo (next character to be read). the lsr[4:2] registers do not physically exist, as the data read from the rx fifo is output directly onto the output data bus, d[4:2], when the lsr is read. therefore, errors in a character are identi?ed by reading the lsr and then reading the rhr. lsr[7] is set when there is an error anywhere in the rx fifo, and is cleared only when there are no more errors remaining in the fifo. reading the lsr does not cause an increment of the rx fifo read pointer. the rx fifo read pointer is incremented by reading the rhr. table 14: line status register bits description bit symbol description 7 lsr[7] fifo data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error, or break indication is in the receiver fifo. this bit is cleared when no more errors are present in the fifo. 6 lsr[6] thr and tsr empty. this bit is the transmit empty indicator. logic 0 = transmitter hold and shift registers are not empty logic 1 = transmitter hold and shift registers are empty 5 lsr[5] thr empty. this bit is the transmit holding register empty indicator. logic 0 = transmit hold register is not empty logic 1 = transmit hold register is empty. the processor can now load up to 64 bytes of data into the thr if the tx fifo is enabled. 4 lsr[4] break interrupt. logic 0 = no break condition (normal default condition) logic 1 = a break condition occurred and associated byte is 00, that is, rx was low for one character time frame. 3 lsr[3] framing error. logic 0 = no framing error in data being read from rx fifo (normal default condition) logic 1 = framing error occurred in data being read from rx fifo, that is, received data did not have a valid stop bit. 2 lsr[2] parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error in data being read from rx fifo 1 lsr[1] overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error has occurred 0 lsr[0] data in receiver. logic 0 = no data in receive fifo (normal default condition) logic 1 = at least one character in the rx fifo
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 25 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos remark: the three error bits (parity, framing, break) may not be updated correctly in the ?rst read of the lsr when the input clock (xtal1) is running faster than 36 mhz. however, the second read is always correct. it is strongly recommended that when using this device with a clock faster than 36 mhz, that the lsr be read twice and only the second read be used for decision making. all other bits in the lsr are correct on all reads. 7.6 modem control register (mcr) the mcr controls the interface with the mode, data set, or peripheral device that is emulating the modem. t ab le 15 shows modem control register bit settings. [1] mcr[7:5] can only be modi?ed when efr[4] is set, that is, efr[4] is a write enable. table 15: modem control register bits description bit symbol description 7 mcr[7] [1] clock select. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 mcr[6] [1] tcr and tlr enable. logic 0 = no action. logic 1 = enable access to the tcr and tlr registers 5 mcr[5] [1] xon any. logic 0 = disable xon any function logic 1 = enable xon any function 4 mcr[4] enable loop-back. logic 0 = normal operating mode logic 1 = enable local loop-back mode (internal). in this mode the mcr[3:0] signals are looped back into msr[7:4] and the tx output is looped back to the rx input internally. 3 mcr[3] op a/ opb control. logic 0 = forces op a/ opb output to high state logic 1 = forces op a/ opb output to low state. in loop-back mode, controls msr[7]. 2 mcr[2] fifo ready enable. logic 0 = disable the fifo rdy register logic 1 = enable the fifo rdy register. in loop-back mode, controls msr[6]. 1 mcr[1] r ts logic 0 = force r ts output to inactive (high) logic 1 = force r ts output to active (low). in loop-back mode, controls msr[4]. if auto- r ts is enabled, the r ts output is controlled by hardware ?ow control. 0 mcr[0] dtr logic 0 = force dtr output to inactive (high) logic 1 = force dtr output to active (low). in loop-back mode, controls msr[5].
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 26 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.7 modem status register (msr) this 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. it also indicates when a control input from the modem changes state. t ab le 16 shows modem status register bit settings per channel. [1] the primary inputs ri, cd, cts, dsr are all active low, but their registered equivalents in the msr and mcr (in loop-back) registers are active high. table 16: modem status register bits description bit symbol description 7 msr[7] [1] cd (active high, logical 1). this bit is the complement of the cd input during normal mode. during internal loop-back mode, it is equivalent to mcr[3]. 6 msr[6] [1] ri (active high, logical 1). this bit is the complement of the ri input during normal mode. during internal loop-back mode, it is equivalent to mcr[2]. 5 msr[5] [1] dsr (active high, logical 1). this bit is the complement of the dsr input during normal mode. during internal loop-back mode, it is equivalent mcr[0]. 4 msr[4] [1] cts (active high, logical 1). this bit is the complement of the cts input during normal mode. during internal loop-back mode, it is equivalent to mcr[1]. 3 msr[3] d cd. indicates that cd input (or mcr[3] in loop-back mode) has changed state. cleared on a read. 2 msr[2] d ri. indicates that ri input (or mcr[2] in loop-back mode) has changed state from low to high. cleared on a read. 1 msr[1] d dsr. indicates that dsr input (or mcr[0] in loop-back mode) has changed state. cleared on a read. 0 msr[0] d cts. indicates that cts input (or mcr[1] in loop-back mode) has changed state. cleared on a read.
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 27 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.8 interrupt enable register (ier) the interrupt enable register (ier) enables each of the six types of interrupt, receiver error, rhr interrupt, thr interrupt, xoff received, or cts/ r ts change of state from low to high. the irq output signal is activated in response to interrupt generation. t ab le 17 shows interrupt enable register bit settings. [1] ier[7:4] can only be modi?ed if efr[4] is set, that is, efr[4] is a write enable. re-enabling ier[1] will not cause a new interrupt if the thr is below the threshold. table 17: interrupt enable register bits description bit symbol description 7 ier[7] [1] cts interrupt enable. logic 0 = disable the cts interrupt (normal default condition) logic 1 = enable the cts interrupt 6 ier[6] [1] r ts interrupt enable. logic 0 = disable the r ts interrupt (normal default condition) logic 1 = enable the r ts interrupt 5 ier[5] [1] xoff interrupt. logic 0 = disable the xoff interrupt (normal default condition) logic 1 = enable the xoff interrupt 4 ier[4] [1] sleep mode. logic 0 = disable sleep mode (normal default condition) logic 1 = enable sleep mode. see section 6.7 sleep mode for details. 3 ier[3] modem status interrupt. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 2 ier[2] receive line status interrupt. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 ier[1] transmit holding register interrupt. logic 0 = disable the thr interrupt (normal default condition) logic 1 = enable the thr interrupt 0 ier[0] receive holding register interrupt. logic 0 = disable the rhr interrupt (normal default condition) logic 1 = enable the rhr interrupt
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 28 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.9 interrupt identi?cation register (iir) the iir is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. t ab le 18 shows interrupt identi?cation register bit settings. the interrupt priority list is shown in t ab le 19 . table 18: interrupt identi?cation register bits description bit symbol description 7:6 iir[7:6] mirror the contents of fcr[0]. 5 iir[5] r ts/ cts low-to-high change of state 4 iir[4] 1 = xoff/special character has been detected 3:1 iir[3:1] 3-bit encoded interrupt. see t ab le 19 . 0 iir[0] interrupt status. logic 0 = an interrupt is pending logic 1 = no interrupt is pending table 19: interrupt priority list priority level iir[5] iir[4] iir[3] iir[2] iir[1] iir[0] source of the interrupt 1 000110 receiver line status error 2 001100 receiver time-out interrupt 2 000100 rhr interrupt 3 000010 thr interrupt 4 000000 modem interrupt 5 010000 received xoff signal/ special character 6 100000 cts, r ts change of state from active (low) to inactive (high)
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 29 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.10 enhanced feature register (efr) this 8-bit register enables or disables the enhanced features of the uart. t ab le 20 shows the enhanced feature register bit settings. 7.11 divisor latches (dll, dlh) these are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. dlh stores the most signi?cant part of the divisor. dll stores the least signi?cant part of the divisor. note that dll and dlh can only be written to before sleep mode is enabled, that is, before ier[4] is set. 7.12 transmission control register (tcr) this 8-bit register is used to store the rx fifo threshold levels to stop/start transmission during hardware/software ?ow control. t ab le 21 shows transmission control register bit settings. tcr trigger levels are available from 0 bytes to 60 bytes with a granularity of four. table 20: enhanced feature register bits description bit symbol description 7 efr[7] cts ?ow control enable. logic 0 = cts ?ow control is disabled (normal default condition) logic 1 = cts ?ow control is enabled. transmission will stop when a high signal is detected on the cts pin. 6 efr[6] r ts ?ow control enable. logic 0 = r ts ?ow control is disabled (normal default condition) logic 1 = r ts ?ow control is enabled. the r ts pin goes high when the receiver fifo halt trigger level tcr[3:0] is reached, and goes low when the receiver fifo resume transmission trigger level tcr[7:4] is reached. 5 efr[5] special character detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. received data is compared with xoff-2 data. if a match occurs, the received data is transferred to fifo and iir[4] is set to a logical 1 to indicate a special character has been detected. 4 efr[4] enhanced functions enable bit. logic 0 = disables enhanced functions and writing to ier[7:4], fcr[5:4], mcr[7:5] logic 1 = enables the enhanced function ier[7:4], fcr[5:4], and mcr[7:5] can be modi?ed, that is, this bit is therefore a write enable 3:0 efr[3:0] combinations of software ?ow control can be selected by programming these bits. see t ab le 4 softw are ? o w control options (efr[0:3]) on page 9 . table 21: transmission control register bits description bit symbol description 7:4 tcr[7:4] rx fifo trigger level to resume transmission (0 bytes to 60 bytes). 3:0 tcr[3:0] rx fifo trigger level to halt transmission (0 bytes to 60 bytes).
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 30 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos remark: tcr can only be written to when efr[4] = 1 and mcr[6] = 1. the programmer must program the tcr such that tcr[3:0] > tcr[7:4]. there is no built-in hardware check to make sure this condition is met. also, the tcr must be programmed with this condition before auto- r ts or software ?ow control is enabled to avoid spurious operation of the device. 7.13 trigger level register (tlr) this 8-bit register is pulsed to store the transmit and received fifo trigger levels used for dma and interrupt generation. trigger levels from 4 to 60 can be programmed with a granularity of 4. t ab le 22 shows trigger level register bit settings. remark: tlr can only be written to when efr[4] = 1 and mcr[6] = 1. if tlr[3:0] or tlr[7:4] are logical 0, the selectable trigger levels via the fifo control register (fcr) are used for the transmit and receive fifo trigger levels. trigger levels from 4 bytes to 60 bytes are available with a granularity of four. the tlr should be programmed for n 4 , where n is the desired trigger level. when the trigger level setting in tlr is zero, the SC68C752B uses the trigger level setting de?ned in fcr. if tlr has non-zero trigger level value, the trigger level de?ned in fcr is discarded. this applies to both transmit fifo and receive fifo trigger level setting. when tlr is used for rx trigger level control, fcr[7:6] should be left at the default state, that is, 00. 7.14 fifo ready register the fifo ready register provides real-time status of the transmit and receive fifos of both channels. the fifo rdy register is a read-only register that can be accessed when any of the two uarts is selected cs = 0, mcr[2] (fifo rdy enable) is a logic 1, and loop-back is disabled. the address is 111. table 22: trigger level register bits description bit symbol description 7:4 tlr[7:4] rx fifo trigger levels (4 to 60), number of characters available. 3:0 tlr[3:0] tx fifo trigger levels (4 to 60), number of spaces available. table 23: fifo ready register bits description bit symbol description 7:6 fifo rdy[7:6] unused; always 0 5 fifo rdy[5] rx fifo b status; related to dma 4 fifo rdy[4] rx fifo a status; related to dma 3:2 fifo rdy[3:2] unused; always 0 1 fifo rdy[1] tx fifo b status; related to dma 0 fifo rdy[0] tx fifo a status; related to dma
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 31 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 8. programmers guide the base set of registers that is used during high-speed data transfer have a straightforward access method. the extended function registers require special access bits to be decoded along with the address lines. the following guide will help with programming these registers. note that the descriptions below are for individual register access. some streamlining through interleaving can be obtained when programming all the registers. table 24: register programming guide command actions set baud rate to value1, value2 read lcr (03), save in temp set lcr (03) to 80 set dll (00) to value1 set dlm (01) to value2 set lcr (03) to temp set xoff-1, xon-1 to value1, value2 read lcr (03), save in temp set lcr (03) to bf set xoff-1 (06) to value1 set xon-1 (04) to value2 set lcr (03) to temp set xoff-2, xon-2 to value1, value2 read lcr (03), save in temp set lcr (03) to bf set xoff-2 (07) to value1 set xon-2 (05) to value2 set lcr (03) to temp set software ?ow control mode to value read lcr (03), save in temp set lcr (03) to bf set efr (02) to value set lcr (03) to temp set ?ow control threshold to value read lcr (03), save in temp1 set lcr (03) to bf read efr (02), save in temp2 set efr (02) to 10 + temp2 set lcr (03) to 00 read mcr (04), save in temp3 set mcr (04) to 40 + temp3 set tcr (06) to value set mcr (04) to temp3 set lcr (03) to bf set efr (02) to temp2 set lcr (03) to temp1
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 32 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos [1] sign here means bit-and. set tx fifo and rx fifo thresholds to value read lcr (03), save in temp1 set lcr (03) to bf read efr (02), save in temp2 set efr (02) to 10 + temp2 set lcr (03) to 00 read mcr (04), save in temp3 set mcr (04) to 40 + temp3 set tlr (07) to value set mcr (04) to temp3 set lcr (03) to bf set efr (02) to temp2 set lcr (03) to temp1 read fifo rdy register read mcr (04), save in temp1 set temp2 = temp1 ef [1] set mcr (04) = 40 + temp2 read ffr (07), save in temp2 pass temp2 back to host set mcr (04) to temp1 set prescaler value to divide-by-1 read lcr (03), save in temp1 set lcr (03) to bf read efr (02), save in temp2 set efr (02) to 10 + temp2 set lcr (03) to 00 read mcr (04), save in temp3 set mcr (04) to temp3 7f [1] set lcr (03) to bf set efr (02) to temp2 set lcr (03) to temp1 set prescaler value to divide-by-4 read lcr (03), save in temp1 set lcr (03) to bf read efr (02), save in temp2 set efr (02) to 10 + temp2 set lcr (03) to 00 read mcr (04), save in temp3 set mcr (04) to temp3 + 80 set lcr (03) to bf set efr (02) to temp2 set lcr (03) to temp1 table 24: register programming guide continued command actions
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 33 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 9. limiting values [1] stresses beyond those listed under t ab le 25 limiting v alues may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. table 25: limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v cc supply voltage - 7 v v i input voltage - 0.3 v cc + 0.3 v v o output voltage - 0.3 v cc + 0.3 v t amb operating ambient temperature in free-air - 40 +85 c t stg storage temperature - 65 +150 c
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 34 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 10. static characteristics [1] meets ttl levels, v il(min) = 2 v and v ih(max) = 0.8 v on non-hysteresis inputs. [2] applies for external output buffers. [3] these parameters apply for d[7:0]. [4] these parameters apply for dtra, dtrb, r tsa, r tsb, rxrd y a, rxrd yb, txrd y a, txrd yb, txa, txb. [5] except xtal2, v ol = 1 v typical. [6] these junction temperatures re?ect simulated conditions. absolute maximum junction temperature is 150 c. the customer is responsible for verifying junction temperature. [7] applies to external clock; crystal oscillator max. 24 mhz. [8] measurement condition, normal operation other than sleep mode: v cc = 3.3 v; t amb =25 c. full duplex serial activity on all two serial (uart) channels at the clock frequency speci?ed in the recommended operating conditions with divisor of 1. table 26: static characteristics tolerance of v cc = 10 % symbol parameter conditions v cc = 2.5 v v cc = 3.3 v and 5 v unit min typ max min typ max v cc supply voltage v cc - 10 % v cc v cc +10% v cc - 10 % v cc v cc +10% v v i input voltage 0 - v cc 0-v cc v v ih high-level input voltage [1] 1.6 - v cc 2.0 - v cc v v il low-level input voltage [1] - - 0.65 - - 0.8 v v o output voltage [2] 0-v cc 0-v cc v v oh high-level output voltage i oh = - 8ma [3] - - - 2.0 - - v i oh = - 4ma [4] - - - 2.0 - - v i oh = - 800 m a [3] 1.85 - - - - - v i oh = - 400 m a [4] 1.85 - - - - - v v ol low-level output voltage [5] i ol =8ma [3] - - - - - 0.4 v i ol =4ma [4] - - - - - 0.4 v i ol =2ma [3] --0.4---v i ol = 1.6 ma [4] --0.4---v c i input capacitance - - 18 - - 18 pf t amb operating ambient temperature - 40 +25 +85 - 40 +25 +85 c t j junction temperature [6] 0 +25 +125 0 +25 +125 c f (i)xtal1 input clock frequency [7] - - 50 - - 80 mhz d clock duty cycle - 50 - - 50 - % i cc supply current f = 5 mhz [8] - - 3.5 - - 4.5 ma i cc(sleep) sleep current - - 200 - - 200 m a
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 35 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 11. dynamic characteristics [1] rclk is an internal signal derived from divisor latch lsb (dll) and divisor latch msb (dlm) divisor latches. [2] applies to external clock; crystal oscillator max 24 mhz. [3] maximum frequency = table 27: dynamic characteristics t amb = - 40 c to +85 c; tolerance of v cc = 10 %, unless speci?ed otherwise. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v and 5 v unit min max min max t d1 r/ w to chip select 10 - 10 - ns t d2 read cycle delay 25 pf load 20 - 20 - ns t d3 delay from cs to data 25 pf load - 77 - 26 ns t d4 data disable time 25 pf load - 15 - 15 ns t d6 write cycle delay 25 - 25 - ns t d7 delay from write to output 25 pf load - 100 - 33 ns t d8 delay to set interrupt from modem input 25 pf load - 100 - 24 ns t d9 delay to reset interrupt from read 25 pf load - 100 - 24 ns t d10 delay from stop to set interrupt - 1t rclk [1] -1t rclk [1] s t d11 delay from read to reset interrupt 25 pf load - 100 - 29 ns t d12 delay from start to set interrupt - 100 - 100 ns t d13 delay from write to transmit start 8t rclk [1] 24t rclk [1] 8t rclk [1] 24t rclk [1] s t d14 delay from write to reset interrupt - 100 - 70 ns t d15 delay from stop to set rxrd y-1t rclk [1] -1t rclk [1] s t d16 delay from read to reset rxrd y - 100 - 75 ns t d17 delay from write to set txrd y - 100 - 70 ns t d18 delay from start to reset txrd y - 16t rclk [1] - 16t rclk [1] s t h2 r/ w hold time from cs 10 - 10 - ns t h3 data hold time 15 - 15 - ns t h4 address hold time 15 - 15 - ns t 1w , t 2w clock cycle period 10 - 6 - ns f xtal clock speed [2] [3] - 48 - 80 mhz t (reset) reset pulse width 200 - 200 - ns t su1 address setup time 10 - 10 - ns t su2 data setup time 16 - 16 - ns t w1 cs strobe width 77 - 30 - ns 1 t 3w -------
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 36 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 11.1 timing diagrams fig 13. general read timing 002aab087 t su1 a0 to a3 cs r/w d0 to d7 t w1 t h4 t d2 t d4 t d1 t d3 valid data valid data valid address valid address fig 14. general write timing 002aab088 a0 to a3 d0 to d7 cs r/w t d1 t su2 t h3 t h2 t d6 t h4 t w1 t su1 valid data valid data valid address valid address
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 37 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos (1) cs timing during a write cycle. see figure 14 . (2) cs timing during a read cycle. see figure 13 . fig 15. modem input/output timing t d7 change of state t d8 t d8 t d9 002aab089 t d8 change of state change of state change of state active active active active active active active change of state rtsa, rtsb dtra, dtrb cs (write) (1) cda, cdb ctsa, ctsb dsra, dsrb irq cs (read) (2) ria, rib fig 16. external clock timing external clock 002aaa112 t 3w t 2w t 1w f xtal 1 t 3w ------- =
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 38 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos fig 17. receive timing d0 d1 d2 d3 d4 d5 d6 d7 active active 16 baud rate clock 002aab090 t d11 next data start bit stop bit parity bit start bit t d10 rxa, rxb irq cs (read) data bits (0 to 7) 5 data bits 6 data bits 7 data bits fig 18. receive ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab091 next data start bit stop bit parity bit t d15 rxa, rxb rxrdya, rxrdyb cs (read) active data ready start bit data bits (0 to 7) active t d16
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 39 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos fig 19. receive ready timing in fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab092 first byte that reaches the trigger level stop bit parity bit t d15 rxa, rxb rxrdya, rxrdyb cs (read) active data ready start bit data bits (0 to 7) active t d16 fig 20. transmit timing d0 d1 d2 d3 d4 d5 d6 d7 active tx ready active 16 baud rate clock 002aab093 t d14 start bit t d12 txa, txb irq cs (write) data bits (0 to 7) active t d13 5 data bits 6 data bits 7 data bits parity bit stop bit next data start bit
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 40 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos fig 21. transmit ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab094 start bit t d17 txa, txb txrdya, txrdyb cs (write) data bits (0 to 7) active d0 to d7 byte #1 t d18 transmitter not ready active transmitter ready parity bit stop bit next data start bit fig 22. transmit ready timing in fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab377 stop bit parity bit t d17 txa, txb cs (write) d0 to d7 start bit data bits (0 to 7) byte #64 txrdya, txrdyb t d18 trigger lead active 5 data bits 6 data bits 7 data bits
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 41 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 12. package outline fig 23. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 42 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 13. soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 13.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 43 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 13.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 28: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 44 of 46 philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 14. abbreviations 15. revision history table 29: abbreviations acronym description cpu central processing unit dma direct memory access fifo first in/first out lsb least signi?cant bit msb most signi?cant bit uart universal asynchronous receiver and transmitter table 30: revision history document id release date data sheet status change notice doc. number supersedes SC68C752B_2 20050428 product data sheet - 9397 750 14963 SC68C752B_1 modi?cations: ? added and motorola m p interface to descriptive title on ?rst page. ? section 2 f eatures on page 1 C ?rst bullet: added with motorola m p interface C second bullet re-written ? added section 19 t r ademar ks on page 45 . SC68C752B_1 20050329 product data sheet - 9397 750 13857 -
philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 9397 750 14963 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 45 of 46 16. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 18. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 19. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. 20. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 28 april 2005 document number: 9397 750 14963 published in the netherlands philips semiconductors SC68C752B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 7 6.1 trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 hardware ?ow control . . . . . . . . . . . . . . . . . . . . 7 6.2.1 auto- r ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2.2 auto- cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 software ?ow control . . . . . . . . . . . . . . . . . . . . 9 6.3.1 rx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3.2 tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3.3 software ?ow control example . . . . . . . . . . . . 11 6.3.3.1 assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5.1 interrupt mode operation . . . . . . . . . . . . . . . . 14 6.5.2 polled mode operation . . . . . . . . . . . . . . . . . . 14 6.6 dma operation . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.1 single dma transfers (dma mode 0/ fifo disable) . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.1.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.1.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.2 block dma transfers (dma mode 1). . . . . . . . 16 6.6.2.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.6.2.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.7 sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.8 break and time-out conditions . . . . . . . . . . . . 17 6.9 programmable baud rate generator . . . . . . . . 17 7 register descriptions . . . . . . . . . . . . . . . . . . . 19 7.1 receiver holding register (rhr). . . . . . . . . . 21 7.2 transmit holding register (thr) . . . . . . . . . . 21 7.3 fifo control register (fcr) . . . . . . . . . . . . . 22 7.4 line control register (lcr) . . . . . . . . . . . . . . 23 7.5 line status register (lsr) . . . . . . . . . . . . . . . 24 7.6 modem control register (mcr) . . . . . . . . . . . 25 7.7 modem status register (msr). . . . . . . . . . . . 26 7.8 interrupt enable register (ier) . . . . . . . . . . . 27 7.9 interrupt identi?cation register (iir). . . . . . . . 28 7.10 enhanced feature register (efr) . . . . . . . . . 29 7.11 divisor latches (dll, dlh) . . . . . . . . . . . . . . . 29 7.12 transmission control register (tcr) . . . . . . . 29 7.13 trigger level register (tlr). . . . . . . . . . . . . . 30 7.14 fifo ready register. . . . . . . . . . . . . . . . . . . . . 30 8 programmers guide . . . . . . . . . . . . . . . . . . . . 31 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33 10 static characteristics . . . . . . . . . . . . . . . . . . . 34 11 dynamic characteristics . . . . . . . . . . . . . . . . . 35 11.1 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 36 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 41 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 42 13.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 42 13.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 43 13.5 package related soldering information . . . . . . 43 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 44 16 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 45 17 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 18 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 19 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 20 contact information . . . . . . . . . . . . . . . . . . . . 45

▲Up To Search▲

Price & Availability of SC68C752B

	To Download SC68C752B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .